It is known that above certain critical temperatures surfaces of compound semiconductors can be impaired, e.g., by distortions and deformations. To avoid such impairments in lithographic structures that have to be transferred onto a wafer, it is also known in the art to seek to simplify lithography. For example, the prior art recommends avoiding as far as possible corners in the same lithographic plane.
Use of different channel widths of transistors is a common practice. The channel length of an MOSFET transistor is at the present time typically around 30 nm, whereas its width (W) is typically much greater. The width determines the current intensity in the transistor for given source, drain and gate voltages.
Therefore, it is usually desirable to design an electronic circuit with transistors having different channel widths. But, in practice it is difficult to obtain different widths with precision because of the resolution limits of lithography. In fact, although it is relatively easy to produce long strip-like structures by lithography, short strips of very controlled dimensions are particularly difficult to fabricate.
US patent application 2008/0251848 teaches a fabrication process aimed at obviating inhomogeneities in performance between the various transistors of a circuit. To do so, this document proposes to make the influence of the environment on the various transistors uniform. More precisely, this document provides that an array of FET transistors be arranged in the form of long strips. The drain and source regions of any one strip then have the same dimensions, being spaced apart by gate regions of fixed dimensions. This document is further described herein.
The resolution limit of the lithography tends to dictate the use of such long strips of transistors having identical dimensions. However, with long strips, the flexibility in designing electronic circuits is then lost since it is no longer possible to vary the geometric width of the various transistors so as to modulate their performance.